1. Field of the Invention
This invention relates to an optoelectronic device chip. More particularly, this invention relates to an optoelectronic device chip having a composite spacer structure, and a method for making the optoelectronic device chip having the composite spacer structure.
2. Description of the Related Art
Digital imaging devices have been widely used in many electronic products nowadays. They are used in, for example, digital cameras, digital video recorders, cellular phones with photographing function, safety-control monitors, etc.
A digital imaging device usually includes an optoelectronic device chip, such as a CCD image sensor chip or a CMOS image sensor chip. Such image sensor chips may be packaged by means of an advanced package technology called “wafer-level chip scale package”, WLCSP. In traditional package technology, a wafer having micro-devices such as electronic devices, electromechanical devices or optoelectronic devices made thereon is first diced into multiple chips, and thereafter the chips are packaged. However, according to WLCSP, micro-devices such as image sensors may be packaged at their “wafer level” (i.e., when they are still on a wafer).
U.S. Pat. No. 6,777,767 issued to Badehi has disclosed a method for such WLCSP. According to Badehi, as shown in FIG. 1 of the present invention, a package layer is prepared which includes a substrate 400 and multiple spacers 406. The spacers 406 are made of a photo resist material such as an epoxy based photo resist, and patterned by a lithography process to become the structure as shown in the figure.
Referring to FIGS. 2(A)-2(E), adhesive 402 is applied to the package layer adjacent and between the spacers 406, so that the package layer may be bonded with another substrate 404 which is provided with multiple micro-devices thereon. After bonding, the substrate 404 is grinded and etched to become thin separate parts 407, and a cavity 405 is defined between the upper substrate layer 400 and the substrate 404 (FIG. 2(B)). An underlying package layer 410 is adhered to the structure via an epoxy layer 408 (FIG. 2(C)). The package layer 410 and epoxy layer 408 are mechanically notched, and thereafter electrical contacts 412 and bumps 414 are formed thereon (FIG. 2(D)). The resulting assembly is diced along the dash lines to yield a plurality of packaged chips as shown in FIG. 2(E).
In applying the abovementioned WLCSP technology to packaging optoelectronic devices such as digital imaging devices, unlike other electronic devices or electromechanical devices, there is a unique concern—the height of the cavity 405 is very critical to optical characteristics of the devices. In a digital imaging device chip, the height of the cavity 405 is the distance between a cover glass and the focus plane. This distance should be precisely controlled for optimum optical performance. In a digital imaging device chip, the thickness tolerance should be within the range of the depth of focus, which depends on the pixel size and the f/number (FNo) of the optical system associated with the imaging device chip. For example, in an optical system with FNo equal to 2.8, the depth of focus of a 3.6 μm sensor (i.e., pixel size 3.6 μm) is about 10.08 μm; the depth of focus of a 2.2 μm sensor is about 6.16 μm; the depth of focus of a 1.8 μm sensor is about 5.04 μm; the depth of focus of a 1.2 μm sensor is about 3.36 μm.
However, according to Badehi, the height of the cavity 405 is determined by the laminated structure thickness of the spacers 406 and the adhesive 402, while the spacers 406 are formed by a lithography process. Such thick photo resist layer (unlike the photo resist layer used for patterning a semiconductor integrated circuit layer, which is typically in the range of about 1 μm) would result in severe wafer uniformity issue, typically ±(10-20)% thickness variation across the wafer due to spin coating and photo resist viscosity. In other words, there would be ±4 μm to ±8 μm thickness variation for a target spacer thickness of 40 μm. Such a huge difference is unacceptable because it would cause severe defocus issue when the pixel size is smaller than 2.2 μm. As an example, FIG. 7 shows the spot sizes at 46/43/40/37/34 μm, respectively, for a case wherein the pixel size is 1.8 μm and the target thickness is 40 μm. As seen from the figure, the spot sizes at 46 μm and 34 μm have become unacceptably large. The larger the spot size is, the worse the MTF (modulation transfer function) performance is. Therefore, it is necessary to develop a new spacer structure so that the thickness variation is within the thickness tolerance, i.e., the depth of focus, for better optical performance uniformity across the wafer.
In addition to the above drawback, the laminated structure formed by the spacer 406 and the adhesive 402 does not provide enough strength to resist tensile or compressive stress, heat, and shearing force. The process steps after the bonding step of FIG. 2(A) may cause the wafer to crack or delaminate during environmental testing.
Accordingly, for optoelectronic devices such as digital imaging devices, an improved WLCSP method providing more robust spacer structure and more accurate control of the spacer thickness, are required.